Power-driven Design of Router Microarchitectures in On-chip Networks

As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-chip communication. The tight delay requirements faced by on-chip networks have resulted in prior microarchitectures being largely performance-driven. While performance is a critical metric, on-chip networks are also extremely power-constrained. In this paper, we investigate on-chip network microarchitectures from a power-driven perspective. We first analyze the power dissipation of existing network microarchitectures, highlighting insights that prompt us to devise several power-efficient network microarchitectures: segmented crossbar, cut-through crossbar and writethrough buffer. We also study and uncover the power saving potential of an existing network architecture: express cube. These techniques are evaluated with synthetic as well as real chip multiprocessor traces, showing a reduction in network power...

• Type: Conference
• Year: 2003
• Where: MICRO
• Authors: Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
• Keywords: Hardware, MICRO 2003, Network Microarchitectures, On-chip Network, On-chip Network Microarchitectures