Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms

The power-efficient implementation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implementing an optimum on-chip memory hierarchy inside the FPGA, and moving the bulk of required memory transfers from the internal memory hierarchy instead of the external memory. Comparisons among implementations with and without this optimization, prove that great power efficiency is achieved while satisfying performance constraints.

• Type: Conference
• Year: 2003
• Where: FPL
• Authors: Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis
• Keywords: External Memory, FPL 2003, Memory Hierarchy, On-chip Memory Hierarchy