A Power Estimation Model for High-Speed CMOS A/D Converters

Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits information from reported designs is presented. The estimator is an analytical expression which is independent of the actual topology used and can easily be updated with new published designs. Experimental results show a good predictor accuracy of better than a factor 2.2 for most designs.

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Erik Lauwers, Georges G. E. Gielen
• Keywords: DATE 1999, Hardware, Power Estimation, Power Estimator, System-level Exploration