430 search results - page 1 / 86 » Power Optimized Combinational Logic Design |
CSREAESA
2003
14 years 7 months ago
2003
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
ICCAD
1996
IEEE
14 years 10 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
CSREAESA
2004
14 years 8 months ago
2004
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
DATE
2000
IEEE
14 years 11 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
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ARVLSI
1995
IEEE
14 years 10 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...