Programmable LDPC Decoder Based on the Bubble-Sort Algorithm

Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardware implementation. Due to this property, a lot of research has been done to find their suitability in different communication media. These codes have been shown to achieve near Shannon-limit performance in Wireless AWGN channels. At the same time these codes can result in significant power reduction in on-chip global and semi-global interconnects. These different applications demand a variety of LDPC coder decoder structures. This paper presents a programmable design for a parallel implementation of an LDPC decoder. The programability implies that this decoder can adapt itself to any arbitrary LDPC code for a variety of applications. This paper also presents two example configurations, with a throughput of 2.28 Gbps and 4.37 Gbps respectively.

• Type: Conference
• Year: 2006
• Where: VLSID
• Authors: Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
• Keywords: Computer Architecture, Error Correcting Codes, Low Density Parity, Low Latency Hardware, VLSID 2006