A radix-10 SRT divider based on alternative BCD codings

In this paper we present the algorithm and architecture of a radix-10 floating-point divider based on an SRT nonrestoring digit-by-digit algorithm. The algorithm uses conventional techniques developed to speed-up radix-2k division such as signed-digit (SD) redundant quotient and digit selection by constant comparison using a carry

• Type: Conference
• Year: 2007
• Where: ICCD
• Authors: Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
• Keywords: Hardware, ICCD 2007, Partial Remainder, Propagate Decimal Adder, Radix-10 Floating-point Divider