ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper we present the algorithm and architecture of a radix-10 floating-point divider based on an SRT nonrestoring digit-by-digit algorithm. The algorithm uses conventional...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Transaction-level modeling (TLM) allows a designer to save functional verification effort during the modular refinement of an SoC by reusing the prior implementation of a module a...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
While Speculative Multithreading (SM) on a Chip Multiprocessor (CMP) has the ability to speed-up hard-toparallelize applications, the power inefficiency of aggressive speculation ...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...
ICCD
2007
IEEE
14 years 7 months ago
2007
IEEE
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...