Rapid Generation of Thermal-Safe Test Schedules

Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn’t necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a lowcomplexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
• Keywords: DATE 2005, Hardware, Power Constrained Test, Test Schedule, Test Scheduling