The reduceron reconfigured

The leading implementations of graph reduction all target conventional processors designed for low-level imperative execution. In this paper, we present a processor specially designed to perform graph-reduction. Our processor

• Type: Conference
• Year: 2010
• Where: ICFP
• Authors: Matthew Naylor, Colin Runciman
• Keywords: Graph Reduction, ICFP 2010, Low-level Imperative Execution, Programming Languages, Sequential Graph Reduction