Reducing parity generation latency through input value aware circuits

1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit errors that occur in the storage components. In order to implement parity logic, multiple levels of XOR gates are used and these XOR trees are known to have high delay. Many produced and consumed values inside a processor hold consecutive zeros and ones in their upper order bits. These values can be represented with less number of bits and hence are termed narrow. In this paper we propose a parity generator circuit design that is capable of generating the parity if the input value is narrow. We show that parity can be generated faster than a regular XOR tree implementation using our design for the values that can be represented using fewer bits. Categories and Subject Descriptors B.7.3 [Integrated Circuits]: Reliability and Testing

• Type: Conference
• Year: 2009
• Where: GLVLSI
• Authors: Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz Ergin
• Keywords: GLVLSI 2009, Parity Bits, Parity Logic, VLSI, Xor Tree