Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors

With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi-threading (RMT) is an attractive approach for concurrent error detection and recovery. However, redundant threads significantly increase the pressure on the processor resources, resulting in dramatic performance impact. In this paper, we propose reducing resource redundancy as a means to mitigate the performance impact of redundancy. In this approach, all the instructions are redundantly executed, however, the redundant instructions do not use many of the resources used by an instruction. The approach taken to reduce resource redundancy is to exploit the runtime profile of the leading thread to optimally allocate resources to the trailing thread in a staggered RMT architecture. The key observation used in this approach is that, even with a small slack between the two threads, many instructions in the leading...

• Type: Conference
• Year: 2006
• Where: HPCA
• Authors: Sumeet Kumar, Aneesh Aggarwal
• Keywords: Computer Architecture, Distinct Redundant Instruction, HPCA 2006, Register Value Reuse, Staggered Rmt Architecture