Reuse-based test access and integrated test scheduling for network-on-chip

In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test data to routers. We present possible solutions to the implementation of this scheme. We also show how the router testing can be scheduled concurrently with core testing to reduce test application time. Experimental results for the ITC’02 SoC benchmarks show that the proposed method can lead to substantial reduction on test application time compared to previous work based on the use of serial boundary scan. The method can also help to reduce hardware overhead.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Chunsheng Liu, Zach Link, Dhiraj K. Pradhan
• Keywords: DATE 2006, Hardware, Test Access, Test Application Time, Test Scheduling