ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency

Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introduce large variations in peak operation among chips, among cores on a single chip, and among microarchitectural blocks within one core. Hence, it will be difficult to only rely on traditional frequency binning to efficiently cover the large variations that are expected. Furthermore, multiple voltage/frequency domains introduce significant hardware overhead and alone cannot address the full extent of delay variations expected in future multi-core systems. In this paper, we present ReVIVaL, which combines two fine-grained post-fabrication tuning techniques—voltage interpolation(VI) and variable latency(VL). We show that the frequency variation between chips, between cores on one chip, and between functional units within cores can be reduced to a very small range. The effectiveness of these techniques are f...

• Type: Conference
• Year: 2008
• Where: ISCA
• Authors: Xiaoyao Liang, Gu-Yeon Wei, David Brooks
• Keywords: Cores, Hardware, ISCA 2008, Large Variations, Process Variations