Runlength Compression Techniques for FPGA Configurations

The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that can significantly reduce this overhead. By using runlength and other compression techniques, files can be compressed by a factor of 3.6 times. Bus transfer mechanisms and decompression hardware are also discussed. This results in a single compression methodology which achieves higher compression ratios than existing algorithms in an off-line version, as well as a somewhat lower quality compression approach which is suitable for on-line use in dynamic circuit generation and other mapping-time critical situations. Configuration Compression Reconfigurable computing is an exciting new area that harnesses the programmable power of FPGAs. In the past, FPGAs were used in applications that required them to be configured only once or a few times. The infrequency in which the FPGAs were programmed meant that these app...

• Type: Conference
• Year: 1999
• Where: FCCM
• Authors: Scott Hauck, William D. Wilson
• Keywords: Compression Reconfigurable Computing, FCCM 1999, FPGA, Reconfigurable Computing, VLSI