Safely exploiting multithreaded processors to tolerate memory latency in real-time systems

A coarse-grain multithreaded processor can effectively hide long memory latencies by quickly switching to an alternate task when the active task issues a memory request, improving overall throughput. However, dynamic switching cannot be safely exploited to improve throughput in hard-real-time embedded systems. The schedulability of a task-set (guaranteeing all tasks meet deadlines) must be determined a priori using offline schedulability tests. Any computation/memory overlap must be statically accounted for. We develop a novel analytical framework that bounds the overlap between computation of a pipeline-resident-task and on-going memory transfers of other tasks. A simple closed-form schedulability test is derived, that only depends on the aggregate computation (C) and memory (M) components of tasks. Namely, the technique does not require specificity regarding the location of memory transfers within and among tasks and avoids searching all task permutations for a specific feasible sch...

• Type: Conference
• Year: 2004
• Where: CASES
• Authors: Ali El-Haj-Mahmoud, Eric Rotenberg
• Keywords: CASES 2004, Coarse-grain Multithreaded Processors, Memory Transfers, Schedulability Test