Scheduling and Module Assignment for Reducing Bist Resources

Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resources that can generate pseudo-random test patterns and or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis a ect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a signi cant reduction in BIST area overhead and hence total area.

• Type: Conference
• Year: 1998
• Where: DATE
• Authors: Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
• Keywords: BIST, Bist Resource, Data Paths, DATE 1998, Hardware