Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in the performance and the reliability of future CMOS devices. Th...
Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mi...
Ubiquitous access to sophisticated internet services from diverse end devices across heterogeneous networks requires the injection of additional functionality into the network to ...
Through clean-slate implementation of two storage optimizations--track-aligned extents and track-aligned RAIDs--this paper shows the values of independent validations. The experie...
- This paper presents a non-scan design-for-testability technique applicable to register-transfer(RT) level data path circuits, which are usually very hard-to-test due to the prese...
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
We propose the Multiple Join Path (MJP) framework for obtaining high quality information by linking fields across multiple databases, when the underlying databases have poor qual...
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures...
—The recently proposed Pocket Switched Network paradigm takes advantage of human social contacts to opportunistically create data paths over time. We examine how effective such a...
Protecting shared sensitive information is a key requirement for today’s distributed applications. Our research uses virtualization technologies to create and maintain trusted d...
Jiantao Kong, Karsten Schwan, Min Lee, Mustaque Ah...