Secure Partial Reconfiguration of FPGAs

SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and practical solutions to improve the security of FPGAs. In this paper, we investigate a method to perform a secure dynamic partial reconfiguration of SRAM FPGAs using embedded processor cores. Two schemes based on hard-wired PowerPC processor core and the MicroBlaze soft processor core have been compared and contrasted in terms of speed and FPGA resource usage. A practical experiment, demonstrating feasibility, performance, and flexibility of both schemes has been conducted using Xilinx ML310 board with Xilinx Virtex-II Pro FPGA.

• Type: Conference
• Year: 2005
• Where: FPT
• Authors: Amir Sheikh Zeineddini, Kris Gaj
• Keywords: FPT 2005, Hard-wired Powerpc Processor, Hardware, Processor Core, SRAM FPGAs