Selective state retention design using symbolic simulation

Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memories loses internal register and RAM states so designers have to weigh up the benefits and costs of implementing state retention on some or all of the power gated subsystems where state recovery has significant real-time or energy cost, compared to resetting the subsystem and re-acquiring state from scratch. Library IP and EDA tools can support state retention in hardware synthesized from standard RTL, but due to the silicon area costs there is strong interest in only retaining certain selective state for example the “architectural state” of a CPU to implement sleep modes. Currently there is no known rigourous technique for checking the integrity of selective state retention, and this is due to the complexity of checking that the correctness of the design is not compromised in any way. The complexity is ex...

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: Ashish Darbari, Bashir M. Al-Hashimi, David Flynn, John Biggs
• Keywords: Architectural State, DATE 2009, Hardware, Selective State Retention, State Retention