Self-calibrating Online Wearout Detection

Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in future technology generations. Physical analysis of device failure mechanisms has shown that most wearout mechanisms projected to plague future technology generations are progressive, meaning that the circuit-level effects of wearout develop and intensify with age over the lifetime of the chip. This work leverages the progression of wearout over time in order to present a low-cost hardware structure that identifies increasing propagation delay, which is symptomatic of many forms of wearout, to accurately forecast the failure of microarchitectural structures. To motivate the use of this predictive technique, an HSPICE analysis of the effects of one particular failure mechanism, gate oxide breakdown, on gates from a standard cell library characterized for a 90 nm process is presented. This gate-level analysis is...

• Type: Conference
• Year: 2007
• Where: MICRO
• Authors: Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke
• Keywords: Failure Mechanism, Future Technology Generations, Gate Oxide, Hardware, MICRO 2007