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SBCCI
2009
ACM
131views VLSI» more  SBCCI 2009»
14 years 3 months ago
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and...
Hagen Sämrow, Claas Cornelius, Frank Sill, An...
DATE
2010
IEEE
170views Hardware» more  DATE 2010»
14 years 4 months ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
14 years 4 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
ISCAS
2006
IEEE
85views Hardware» more  ISCAS 2006»
14 years 5 months ago
Effective tunneling capacitance: a new metric to quantify transient gate leakage current
— In this paper we propose a new metric called “effective tunneling capacitance” (Ct eff ) to quantify the transient swing in the gate leakage (gate oxide tunneling) current ...
Elias Kougianos, Saraju P. Mohanty
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 5 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
MICRO
2007
IEEE
79views Hardware» more  MICRO 2007»
14 years 5 months ago
Self-calibrating Online Wearout Detection
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in fu...
Jason A. Blome, Shuguang Feng, Shantanu Gupta, Sco...