Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM

Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source voltage can significantly increase data flipping in standby mode (Hold Failures) resulting in faulty memories. This imposes serious concerns in reducing standby power with source-bias. In this paper, we analyze the effect of source bias on hold failures under both inter-die and intra-die variations. We propose a selfcalibrating SRAM for aggressively reducing leakage while maintaining the hold failures under control. Categories and Subject Descriptors B.3.1 [Semiconductor memories]: Static memory (SRAM) General Terms Algorithms, Design, Experimentation Keywords Adaptive source biasing, hold failures, low power SRAM

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy
• Keywords: DAC 2006, Design Automation, Hold Failures, Low Power Sram, SRAM Arrays