Semi-detailed bus routing with variation reduction

A bus routing algorithm is presented which not only minimizes wire length but also selects the bits in the bus to avoid twisting and conflicts. The resulting bus routes are regular, thus having strong immunity to variations. Minimization for wire length/delay differences between different bits is also implemented. The algorithm is fast, which allows for being embedded in floorplanning and other physical design algorithms.

• Type: Conference
• Year: 2007
• Where: ISPD
• Authors: Fan Mo, Robert K. Brayton
• Keywords: Bus Routes, Bus Routing Algorithm, Hardware, ISPD 2007, Wire Length/delay Differences