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ISPD
2007
ACM
76views Hardware» more  ISPD 2007»
14 years 17 days ago
Semi-detailed bus routing with variation reduction
A bus routing algorithm is presented which not only minimizes wire length but also selects the bits in the bus to avoid twisting and conflicts. The resulting bus routes are regula...
Fan Mo, Robert K. Brayton
ASPDAC
2008
ACM
150views Hardware» more  ASPDAC 2008»
14 years 1 months ago
Bus-aware microarchitectural floorplanning
Abstract-- In this paper we present the first bus-aware microarchitectural floorplanning. Our goal is to study the impact of bus routability on other important floorplanning object...
Dae Hyun Kim, Sung Kyu Lim
ICCD
2008
IEEE
124views Hardware» more  ICCD 2008»
14 years 8 months ago
Global bus route optimization with application to microarchitectural design exploration
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...
Dae Hyun Kim, Sung Kyu Lim