SEP: Simulation framework to evaluate digital hardware architectures

Know-how is the most useful mean for designing new processors before a complete hardware description. The integration rate is increasing very quickly and the timeto-market has to be dramatically reduced because of the rapid evolution of technology. Therefore, reuse and rapid-prototyping are definitely a major issue to integrate existing architectures and to design new ones. SEP is an object-oriented framework which attends these problems. This paper intends to show major problems and solutions in simulation due to our simplification choices and in particular due to a not typed specification. It also presents the service feature which is a major enhancement to SEP and allow some validation of static properties about the rapidprototyped model and its associated instruction-set. In this paper some examples related to the modelling of an industrial bi-core architecture from VLSI Technology

• Type: Conference
• Year: 2000
• Where: ESM
• Authors: Frédéric Mallet, Fernand Boéri, Jean-François Duboc
• Keywords: Complete Hardware Description, ESM 2000, Industrial Bi-core Architecture, Major Issue, Modeling And Simulation