Signal Sampling Based Transition Modeling for Digital Gates Characterization

Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%.

• Type: Conference
• Year: 2004
• Where: PATMOS
• Authors: Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa
• Keywords: Characterization, Current Characterization Methods, PATMOS 2004, Variable Input Transition