Simulation acceleration of transaction-level models for SoC with RTL sub-blocks

Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks. Conventional simulation accelerators synchronize the progresses of simulator and accelerator at every simulation time, which results in poor performance by splitting transactions on the simulator-to-accelerator channel into pieces. Occasional synchronization with predictions and recoveries makes it possible to merge multiple transfers yielding substantial performance gain compared to the conventional method.

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung
• Keywords: Accelerator Models, ASPDAC 2005, Conventional Simulation Accelerators, Hardware, Simulator