Sciweavers

    ASPDAC
    2005
    ACM
    79views Hardware» more  ASPDAC 2005»
    Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
    14 years 1 months ago
    Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
    Download  vswww.kaist.ac.kr
    Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
    Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.