A simulation methodology for reliability analysis in multi-core SoCs

Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to higher temperature and adverse effects on reliability. In this paper, we introduce a simulation methodology to analyze reliability of multi-core SoCs. The proposed simulator is the first to provide system-on-chip level fine-grained reliability analysis. We use our simulation methodology to study the reliability effects of design choices such as thermal packaging and placement, as well as runtime events such as power management policies and workload distributions. Categories and Subject Descriptors: B.8.0 [Performance and Reliability]: General; C.4 [Performance of Systems]: Modeling Techniques. General Terms: Reliability, Measurement.

• Type: Conference
• Year: 2006
• Where: GLVLSI
• Authors: Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli
• Keywords: GLVLSI 2006, Level fine-grained Reliability, Reliability Effects, Simulation Methodology, VLSI