Simultaneous scheduling and binding for power minimization during microarchitecture synthesis

ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the eect of long interconnects and buses, compared to that of gates, on the overall performance, and energy of systems [13]. Consequently, we propose a RT level design technique to reduce the energy dissipated in switching of the buses ( 40% of the on-chip power [13]) in the synthesized microarchitectures. This is accomplished by judiciously binding/scheduling data transfers in a Control Data Flow Graph (CDFG) onto buses in the design. The algorithm considers (i) correlations between data transfers, (ii) constraints on system performance, and (iii) constraints on the number of buses. Simulations on benchmarks show that best-energy designs are up to 75% energy-ecient visa-vis the worst-energy designs. Further, best-energy designs are up to 45% more energy-ecient than the best-delay designs.

• Type: Conference
• Year: 1995
• Where: ISLPED
• Authors: Aurobindo Dasgupta, Ramesh Karri
• Keywords: Data Flow Graph, Data Transfers, Hardware, ISLPED 1995, RT Level Design