Size-Constrained Code Placement for Cache Miss Rate Reduction

In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. We have previously proposed a code placement method which minimizes miss rates of instruction caches [10], but it makes code size larger. In most cases, code size is a tight design constraint. In this paper, we propose a size-constrained code placement method which minimizes cache miss rates under constraint on code size given by system designers. Experimental results show that the sizeconstrained code placement method achieves 36% decrease

• Type: Conference
• Year: 1996
• Where: ISSS
• Authors: Hiroyuki Tomiyama, Hiroto Yasuura
• Keywords: Code Placement Method, Code Size, Hardware, ISSS 1996, Miss Rates