Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing

This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The temporal channel for the Viterbi receiver and the beamformer weights for the CCI rejection are estimated jointly by optimizing a suitable cost function for separable space-time channels. By taking into account nowadays integration capabilities provided by FPGA (Field Programmable Gate Array), it is demonstrated the feasibility of a single chip JSTE solution based on three processor architecture for carrier beamforming, equalization and demodulation.

• Type: Conference
• Year: 2000
• Where: DATE
• Authors: U. Girola, A. Picciriello, D. Vincenzoni
• Keywords: DATE 2000, Hardware, Separable Space-time Channels, Single Chip, Single Chip Implementation