Snow 2.0 IP Core for Trusted Hardware

Stream ciphers are a promising technique for encryption in trusted hardware. ISO/IEC standardization is currently under way and SNOW 2.0 is one of the remaining candidates. Its software implementation is widely examined; this paper discusses the hardware implementation as IP core on a FPGA platform. The area consumption is roughly equivalent to that of a commercial floating-point unit, and the ratio of throughput and effective slice usage is close to 3.5. This allows the IP core to be instantiated in a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.

• Type: Conference
• Year: 2005
• Where: FPL
• Authors: Wenhai Fang, Thomas Johansson, Lambert Spaanenburg
• Keywords: Area Consumption, FPL 2005, IP Core, Slice Usage