SOC Testing Methodology and Practice

Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIST), etc. The chip has been fabricated and tested successfully by our approach. Test results justify that short test integration cost, short test time, and small area overhead can be achieved. To support SOC testing, a memory BIST compiler and an SOC testing integration system have been developed.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Cheng-Wen Wu
• Keywords: DATE 2005, Hardware, Short Test, SOC Test Integration, Test Io Reduction