Software-based instruction caching for embedded processors

While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories instead. These are simple array memory structures that are directly addressed and explicitly managed by software. Compared to hardware caches of the same data capacity, they are smaller, have shorter access times and consume less energy per access. Access times are also easier to predict with simple memories since there is no possibility of a “miss.” On the other hand, they are more difficult for the programmer to use since they are not automatically managed. In this paper, we present a software system that allows all or part of an SRAM or scratchpad memory to be automatically managed as a cache. This system provides the programming convenience of a cache for processors that lack dedicated caching hardware. It has been implemented for an actual processor and runs on real hardware. Our results show that ...

• Type: Conference
• Year: 2006
• Where: ASPLOS
• Authors: Jason E. Miller, Anant Agarwal
• Keywords: ASPLOS 2006, Hardware Cache, Instruction Cache, Memory Structures, Programming Languages