A SRAM-based Architecture for Trie-based IP Lookup Using FPGA

Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbalanced memory allocation over the pipeline stages. This has been identified as a major challenge for pipelined solutions. In this paper, an IP lookup rate of 325 MLPS (millions lookups per second) is achieved using a novel SRAM-based bidirectional optimized linear pipeline architecture on Field Programmable Gate Array, named BiOLP, for tree-based search engines in IP routers. BiOLP can also achieve a perfectly balanced memory distribution over the pipeline stages. Moreover, by employing caching to exploit the Internet traffic locality, BiOLP can achieve a high

• Type: Conference
• Year: 2008
• Where: FCCM
• Authors: Hoang Le, Weirong Jiang, Viktor K. Prasanna
• Keywords: FCCM 2008, Hardware, IP Lookup Rate, Pipeline Stages, Unbalanced Memory Allocation