Static power minimization in current-mode circuits

-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in, a current comparator circuit. Power reduction is achieved by turning off the redundant comparator circuits using a switch-architecture. Simulations are carried-out for current-mode flash ADC designs and literal generatingcircuits for MVL to validatethe method.

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: M. S. Bhat, H. S. Jamadagni
• Keywords: ASPDAC 2005, Comparator Circuits, Current Comparator, Current Comparator Circuit