Statistical Leakage and Timing Optimization for Submicron Process Variation

Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective design methods have been proposed. However, due to the exponential relation of subthreshold current with process parameters, such as, the effective gate length, oxide thickness and doping concentration, process variations can severely affect both power and timing yields of the designs obtained by those methods. In this paper, we propose a mixed integer linear programming method for dual-Vth design that minimizes the leakage power and circuit delay in a statistical sense such that the impact of process variation on the respective yields is minimized. The experimental results show that 30% more leakage power reduction can be achieved by using statistical approach when compared with the deterministic approach.

• Type: Conference
• Year: 2007
• Where: VLSID
• Authors: Yuanlin Lu, Vishwani D. Agrawal
• Keywords: Computer Architecture, Leakage Power, Leakage Power Reduction, Total Power Consumption, VLSID 2007