Statistical technology mapping for parametric yield

The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by variability because of its exponential dependence on the highly varying transistor channel length and threshold voltage. This paper describes the new technology mapping algorithm that performs library binding to maximize parametric yield limited both by timing and power constraints. This is the first work that rigorously treats variability in circuit leakage power and delay within logic synthesis. Experiments show that moving the concerns about variability into logic synthesis is justified. The results on industrial and public benchmarks indicate that, on average, the reduction in stand-by power can be up to 26% and can be as high as 50% for some benchmarks. The reduction is purely due to a more effective decision-making of the mapping algorithm, and is achieved without a timing parametric yield loss. Alterna...

• Type: Conference
• Year: 2005
• Where: ICCAD
• Authors: Ashish Kumar Singh, Murari Mani, Michael Orshansky
• Keywords: Hardware, ICCAD 2005, Leakage Power Constraints, Parametric Yield Losses, Timing Parametric Yield