A Study on Impact of Leakage Current on Dynamic Power

— Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now become comparable to the switching current. Traditionally, dynamic power and leakage power are computed separately. Dynamic power computation does not include leakage from nonswitching nodes. In this paper, we show that in upcoming 45nm technology, leakage from non-switching nodes can account for as much as 38% of total dynamic current. Hence leakage from nonswitching nodes can not be neglected during dynamic power computation. To facilitate this study on large benchmark circuits on which spice level simulation is impractical, we created a compact simulation model for modeling various pattern dependent leakage currents to allow leakage computation at gate level. Using a simulation based experiment we compare leakage and switching currents on ISCAS-85 benchmark circuits. The experiments are based on Berkeley Predi...

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu
• Keywords: Dynamic Power Computation, ISCAS 2007, Leakage Currents, Leakage Power