A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies

— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra-low voltages. Therefore, to operate cells in the subthreshold regime, new cell structures needs to be explored. Towards this, we present a single-ended I/O (SEIO) bit-line latch style 7-transistor static random access memory (SRAM) cell (7T-LSRAM) as an alternative for nanometer CMOS technology which can function in ultra-low voltage regime. Compared to existing 6-transistor (6T) cell or 10-transistor cell design, the proposed cell has 2X improved read stability and ¿ ± better write-ability at lower supply voltage. Furthermore, the 7TLSRAM has improved process variation tolerance. The area analysis shows that there is ½ ± increase in area penalty compared to the standard 6T cell, however the improved performance and process variation tolerance could justify the overhead.

• Type: Conference
• Year: 2008
• Where: SOCC
• Authors: Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
• Keywords: Cell, Cell Design, Education, SOCC 2008, Ultra-low Voltage