Synthesis of Asynchronous Circuits Using Early Data Validity

Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable state until necessary wire transitions trigger an event to occur. This avoids synchronizing events using a global clock tree, which can consume a large amount of energy. The need for low power and high performance circuits leads to investigation of various asynchronous design styles. The work presented here provides an overview and novel implementation of synthesizing asynchronous circuits using an early data validity protocol. Conventional asynchronous tools synthesize circuits using a broad data validity protocol, which leads to simple circuits, but non-overlapped sequencing of consecutive operations. The early protocol requires data to be valid for a shorter period, allowing consecutive operations to overlap phases. The resulting circuits have a potential increase in performance by allowing greater concurrency...

• Type: Conference
• Year: 2005
• Where: VLSID
• Authors: Nitin Gupta, Doug A. Edwards
• Keywords: Asynchronous Circuit Design, Asynchronous Circuits, Computer Architecture, Tools Synthesize Circuits, VLSID 2005