Synthesis of high-performance packet processing pipelines

Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We propose a high-level synthesis technique for a new model for representing packet editing functions. Experiments show our circuits achieve a throughput of up to 40Gb/s on a commercially available FPGA device, equal to state-of-the-art implementations. Categories and Subject Descriptors B.6.3 [Hardware]: Logic Design--Design Aids General Terms Algorithms Keywords Packet processors, Networking, FPGAs, high-level synthesis

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
• Keywords: Available Fpga Device, DAC 2006, Design Automation, Keywords Packet Processors, Packet Editing Functions