Synthesis of Instruction Sets for Pipelined Microprocessors

We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitecture. In addition, the assembly code is generated to show how the application can be compiled with the synthesized instruction set. The design of instruction sets is formulated as a modified scheduling problem. A binary tuple is proposed to model the semantics of instructions and integrate the instruction formation process into the scheduling process. A simulated annealing scheme is used to solve for the schedules. Experiments have shown that the approach is capable of synthesizing powerful instructions for modern pipelined micro-processors. The synthesis algorithm ran with reasonable time and a modest amount of memory for large benchmarks.

• Type: Conference
• Year: 1994
• Where: DAC
• Authors: Ing-Jer Huang, Alvin M. Despain
• Keywords: Computer Architecture, DAC 1994, Instruction Formation Process, Instruction Sets, Modern Pipelined Micro-processors