Synthesis for Manufacturability: A Sanity Check

As we move towards nanometer technology, manufacturing problems become overwhelmingly difficult to solve. Presently, optimization for manufacturability is performed at a post-synthesis stage and has been shown capable of reducing manufacturing cost up to 10%. As in other cases, the abstraction layer where optimization is applied is expected to yield substantial gains. This paper focuses on a new approach to design for manufacturability: logic synthesis for manufacturability. This methodology consists of replacing the traditional area-driven technology mapping with a new manufacturability-driven one. We leverage existing logic synthesis tools to test our method. The results obtained by using STMicroelectronics 0.13

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli
• Keywords: DATE 2004, Hardware, Logic Synthesis, Logic Synthesis Tools, Manufacturing Cost