Synthesis methodology for built-in at-speed testing

We discuss a new synthesis flow, which offers the ability to do easy delay testing almost free in terms of its impact on speed and area as compared to corresponding implementations with standard cells. The methodology uses pre-charged PLAs and bundled routing to produce a completion signal, which is guaranteed to lie on all critical paths. We give a non-delay testing method for ensuring that all matched delays of the completion signal are always slower than on any data computation. The design of the matched delays can be controlled tightly since they are internal to the PLAs, which are regular structures.

• Type: Conference
• Year: 2005
• Where: ICCAD
• Authors: Yinghua Li, Alex Kondratyev, Robert K. Brayton
• Keywords: Completion Signal, Easy Delay Testing, Hardware, ICCAD 2005, Pre-charged Plas