Synthesis of Power Efficient Systems-on-Silicon

We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in three steps: minimization of instruction cache misses, placement of frequently executed sequential basic blocks of code in consecutive Gray code addressed memory locations, and processor and cache applicationdriven selection for low-power. In order to bridge the gap between the profiling and modeling tools from the two traditionally disjoint synthesis domains (architecture and CAD), we developed a new synthesis and evaluation platform. The platform integrates the existing modeling, profiling, and simulation tools with the developed system-level synthesis tools. The effectiveness of the approach is demonstrated on a variety of modern industrial-strength multimedia and communication applications.

• Type: Conference
• Year: 1998
• Where: ASPDAC
• Authors: Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith
• Keywords: ASPDAC 1998, Developed System-level Synthesis, Disjoint Synthesis Domains, Hardware, Modular Synthesis Approach