Sciweavers

ASPDAC
1998
ACM
72views Hardware» more  ASPDAC 1998»
14 years 3 months ago
Space- and Time-Efficient BDD Construction via Working Set Control
Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of proto...
Bwolen Yang, Yirng-An Chen, Randal E. Bryant, Davi...
ASPDAC
1998
ACM
97views Hardware» more  ASPDAC 1998»
14 years 3 months ago
A Novel Design Assistant for Analog Circuits
 This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer d...
Markus Wolf, Ulrich Kleine, Frédéric...
ASPDAC
1998
ACM
107views Hardware» more  ASPDAC 1998»
14 years 3 months ago
VLSI for Multimedia U-NII WLANs
- This paper summarizes aspects of the VLSI development of a high-speed wireless local area network (WLAN). The implications for system-on-achip designs are summarized.
Neil Weste, David J. Skellern, Terry Percival
ASPDAC
1998
ACM
119views Hardware» more  ASPDAC 1998»
14 years 3 months ago
Integer Programming Models for Optimization Problems in Test Generation
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
João P. Marques Silva
ASPDAC
1998
ACM
65views Hardware» more  ASPDAC 1998»
14 years 3 months ago
A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
Miyako Tandai, Takao Shinsha
ASPDAC
1998
ACM
112views Hardware» more  ASPDAC 1998»
14 years 3 months ago
Real Time Fault Injection Using Logic Emulators
A hardware based approach to Fault Emulation independent of the logic emulation system in use has been developed and is presented in this paper. Fault injection into a targetted c...
Reza Sedaghat-Maman, Erich Barke
ASPDAC
1998
ACM
92views Hardware» more  ASPDAC 1998»
14 years 3 months ago
A New Design for Double Edge Triggered Flip-flops
-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET fl...
Massoud Pedram, Qing Wu, Xunwei Wu