Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of proto...
Bwolen Yang, Yirng-An Chen, Randal E. Bryant, Davi...
This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer d...
- This paper summarizes aspects of the VLSI development of a high-speed wireless local area network (WLAN). The implications for system-on-achip designs are summarized.
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
A hardware based approach to Fault Emulation independent of the logic emulation system in use has been developed and is presented in this paper. Fault injection into a targetted c...
-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET fl...