System LSI: Challenges and Opportunities

End of CMOS scaling has been discussed in many places since the late 90's. Even if the end of CMOS scaling is irrelevant, it is for sure that we are facing a turning point in semiconductor business. In this paper, challenges and opportunities of system LSI are discussed from three levels of perspectives. Transistor Level (Physics) What will happen if we continue to scale a CMOS device? Gate controllability will be degraded. If gate oxide thickness is kept constant in order to suppress gate leakage, and if channel length is scaled further, potential of silicon surface near the source that is associated with VTH is lowered by depletion layer capacitance of the drain (CD), as well as gate capacitance (CG). When CD is not small enough compared to CG, MOSFET behaves like a resistor, not a transistor. In other words, MOSFET does not turn off sufficiently. On top of that, leakage from gate is rapidly increasing. It should be noted that Ioff dependence on temperature is diminishing as te...

• Type: Journal
• Year: 2006
• Where: IEICET
• Authors: Tadahiro Kuroda
• Keywords: CMOS, Gate, IEICET 2006, Silicon