Temperature-aware test scheduling for multiprocessor systems-on-chip

—Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integrated circuit (IC) temperatures. This has the potential to damage ICs and cause good ICs to be discarded due to temperature-induced timing faults. We first study the power impact of scan chain testing for the ISCAS89 benchmarks. We find that

• Type: Conference
• Year: 2008
• Where: ICCAD
• Authors: David R. Bild, Sanchit Misra, Thidapat Chantem, Prabhat Kumar, Robert P. Dick, Xiaobo Sharon Hu, Li Shang, Alok N. Choudhary
• Keywords: Damage Ics, Hardware, ICCAD 2008, Scan Chain Testing